Esta Página em Português  

Go to: Main Menu, Content, Options, Login.

Contextual Help  
Escola Superior de Tecnologia de Setúbal Secretaria Académica - informações
You are at: Start > Programmes > Disciplinas > LEEC31141
Main Menu
Validation





Esqueceu a sua senha de acesso?
ESTSetúbal map
Edifício ESTS Bloco A Edifício ESTS Bloco B Edifício ESTS Bloco C Edifício ESTS Bloco D Edifício ESTS Bloco E Edifício ESTS BlocoF Interactive campus map. Click on a specific buiding.

Computer Architecture

Scholar Year: 2019/2020 - 1S

Code: LEEC31141    Acronym: AC
Scientific Fields: Electrónica e Telecomunicações
Section/Department: DEE - Department of Electrical Engineering

Courses

Acronym N. of students Study plan Curricular year ECTS Contact time Total Time
EEC 13 6,0 90 162,0

Teaching weeks: 15

Head

TeacherResponsability
Ana Luísa Lopes AntunesHead

Weekly workload

Hours/week T TP P PL L TC THE EL OT OT/PL TPL S
Type of classes 2 4

Lectures

Type Teacher Classes Hours
Theorethical and Practical classes Totals 1 2,00
Ana Antunes   2,00
Prática Laboratorial Totals 1 4,00
Ana Antunes   4,00

Teaching language

Portuguese

Intended learning outcomes (Knowledges, skills and competencies to be developed by the students)

To study the concepts associated with the architecture of personal computers, regarding the organization of the hardware, control of its operation and interface with the exterior.

Syllabus

1- Architecture of a microcomputer
Basic concepts. Structure of a computer. The von Neumann CPU. Generic structure of a CPU. Data Processing Unit. Control unit. Instruction set. Addressing modes. Pipelining. RISC architecture.
2- Memory system
Concepts of memory hierarchy. Cache memory. Cache project elements. Virtual memory. External memory.
3- Buses and peripherals
Buses. PCI bus. I / O and I / O channels (USB, Ethernet, wireless). DMA. Peripherals (graphical interface, keyboard, mouse).
4- Performance measures of processors and computers
Traditional measures. Benchmarks. Evaluation of results. Law of Amdahl.
5- Parallel Processing
Multicore architectures. Coherence between caches. Multicore integrated circuits.


Demonstration of the syllabus coherence with the UC intended learning outcomes

1 - Theoretical classes with presentation of the material with the support of slides and practical cases.

2 - Laboratory classes where a project is carried out that allows the integration of a complete sensor acquisition, collection, coordination and control system with the capacity to store data and control or share distributed information.

Demonstration of the teaching methodologies coherence with the curricular unit's intended learning outcomes

This curricular unit is evaluated through a practical component and a theoretical component.

The student gets approval by doing the laboratory part and the tests or the exam.

Theoretical component:
The dates of the exams will be established by the ESTS Pedagogical Council.
Test dates are set during the first TP classes.
The minimum grade in the theoretical component is 10 values.

Assessment methodologies and evidences

60% L + 40% P
P - Project note.
T - average of the grades obtained in the tests or grade of the exam.
Minimum marks of 10 in L and T components.
Project:
Although it is intended to implement an open environment for ideas and methodologies, it is necessary to have some general rules:
• Each project class will last 2 hours.
• The project work will be carried out by groups of four or five students.
• Each group must present a work proposal by October 14, 2018.
• In this proposal there must be a list of the components necessary to carry out the project and its availability.
• Follow-up meetings will be held during the semester.
• Students can not miss more than 3 project classes. It is necessary to sign an attendance sheet during class.
• Each group of students must register in advance in a laboratory shift.
• The project must be delivered by January 20, 2019.
• There will be an evaluation of 2nd season, on a date to be defined, but for a maximum score of 14 points.
• The following items must be delivered:
1. An article with 4 pages in format to be defined;
2. A printed A2 poster that mirrors the work done;
3. A functional prototype.
Prototyping boards are not allowed to be delivered. All hardware developed must be mounted on printed circuit boards and within suitable boxes.
PCBs can be machined by the laboratory technician. For the construction of the boxes, 3D printers from ESTSetúbal can be used. The lab technician will provide a time slot for ordering PCBs and supporting 3D printing.
• The final evaluation of the project will have two components:
1. Functional demonstration of the prototype;
2. Discussion about the work.
Since the project has several strengths and since the groups have 4/5 elements, it is natural that there be distribution of tasks by the elements of the group. In this way, it is assumed that each element of the group has a greater knowledge about one or several specific elements of the project. However, all elements of the group have to have a comprehensive knowledge of all aspects of the work performed.
3. The final evaluation will reflect the quality of the work performed and the performance of each group member in the discussion.
4. The final evaluation is individual (there will not be a project note).

Attendance system

In laboratories there is a minimum attendance of 75%.

Assement and Attendance registers

Description Type Time (hours) End Date
Attendance (estimated)  Classes  90
Preparation of the project, presentation and tests  Work  70
Tests/Exams  Test/Exam  8
  Total: 168

Primary Bibliography

William Stallings;Computer Organization and Architecture, 10th edition, Global Edition, 2016. ISBN: 1-292-09685-3
Andrew S. Tanenbaum;Structured Computer Organization, 6th edition, Pearson, 2013. ISBN: 0-273-76924-3
Options
Page generated in: 2026-04-09 to 20:15:00