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Computing Systems Architecture

Scholar Year: 2019/2020 - 1S

Code: SEC10    Acronym: ASC
Scientific Fields: Engenharia e Técnicas Afins
Section/Department: DEE - Department of Electrical Engineering

Courses

Acronym N. of students Study plan Curricular year ECTS Contact time Total Time
IPESEC 6,0 162,0
TSPSEC 23 6,0 162,0

Teaching weeks: 15

Head

TeacherResponsability
Rui Manuel Carvalho dos Santos de Azevedo AntunesHead

Weekly workload

Hours/week T TP P PL L TC THE EL OT OT/PL TPL S
Type of classes 4

Lectures

Type Teacher Classes Hours
Theorethical and Practical classes Totals 1 4,00
Rui Antunes   6,00

Teaching language

Portuguese/English

Intended learning outcomes (Knowledges, skills and competencies to be developed by the students)

At the theoretical level, this course aims to provide students with the knowledge of digital systems and computer architecture.
At the practical level, students are expected to familiarize themselves with breadboarding and programmable logic techniques, to know the most common digital components, to develop synthesis and circuit analysis capabilities.

Syllabus

1. Boolean algebra
2. Basis of numbering
3. Combinatorial logic
4. Sequential logic
5. Single Microprocessor
6. Architecture of a Personal Computer

Software

Xilinx

Deeds


Demonstration of the syllabus coherence with the UC intended learning outcomes

Theoretical-practical classes: In the theoretical-practical classes are taught the basic concepts of each of the themes of the program. For this purpose, systematic use is made of the presentation of examples and the resolution of illustrative exercises.
Laboratory classes: in laboratory classes the student performs laboratory work and acquires complementary knowledge through experimentation.

Demonstration of the teaching methodologies coherence with the curricular unit's intended learning outcomes

There are two components of evaluation: a theoretical and a laboratory. The theoretical evaluation can be obtained by performing the test (s) (the final minimum grade is 9.5 values). The laboratory evaluation consists of laboratory work. Each laboratory work is evaluated according to the student's performance in the respective classes and the presented report. All laboratory work and reports are required. The assessment component will only be completed when the deadlines have been met and after all components and other materials requested in the laboratory have been returned. Failure to submit one or more laboratory work implies disregard for discipline.

Assessment methodologies and evidences

NF = 0.6xL + 0.4xT
on what:
L = Average laboratory work
T = Mean of the test
L> = 9.50; T> = 9.50

Assement and Attendance registers

Description Type Time (hours) End Date
Attendance (estimated)  Classes  0
  Total: 0

Primary Bibliography

Victor Nelson, H. Troy Nagle, Bill Carroll, J. David Irwin;Digital Logic Circuit Analysis and Design, Prentice Hall. ISBN: 0-13-463894-8
Guilherme Arroz;Arquitetura de Computadores. ISBN: 9789728469542
Mário Serafim Nunes;Sistemas Digitais, Editorial Presença

Observations

The URL of the page will be maintained after updating the Moodle materials of support.
Attendance: Mondays, 14h30-17h30

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